For the purpose of miniaturization, large capacity and high integration in semiconductor devices, a process of forming a multi-layer metal line for electrically connecting elements may be required after a transistor, bit line, and capacitor, etc. of the semiconductor device are formed. The transistor includes a MOS transistor having a short channel length. In order to prevent the short-channel effect, the source/drain region of the transistor may be formed to have a lightly doped drain (LDD) region and a Heavily Doped Drain (HDD) region. A CMOS device refers to a device having both a pMOS transistor and an nMOS transistor formed on one semiconductor substrate.
FIGS. 1a and 1b are process cross-sectional views illustrating a related method of forming a 130 nm semiconductor device. Referring to FIG. 1a, Shallow Trench Isolation (STI) regions 2 for isolating elements are formed in a semiconductor substrate 1. The semiconductor substrate 1 is coated with a photoresist which is patterned by exposure and development, forming a first mask 30 through which a pMOS region is opened. Phosphorus (P) or other n type impurity is implanted into the pMOS region to sequentially form an n type well 3 and an n type field stop layer 4. After the first mask 30 is removed, a photoresist is coated again as illustrated in FIG. 1b. The photoresist is patterned by exposure and development to form a second mask 31 through which the nMOS region is opened. A p type impurity is implanted into the exposed nMOS region using the second mask 31, forming a p type well 5 and a p type field stop layer 6. The photoresists may be coated over the first mask 30 and the second mask 31 to a thickness of approximately 0.85 μm to use as a mid ultraviolet (MUV) photoresist (PR) in 130 nm devices.
In the related 130 nm device formed as described above, the photoresist used as an LDD implant mask employs MUV PR having a thickness of 0.85 μm. As the design rules of the LDD implant are adapted for 90 nm processes, the active area of the implant layer (the portion opened to perform the actual implant) is significantly reduced compared with 130 nm devices. PRs used in 90 nm and 130 nm processes cannot be used interchangeably. Previously, there has been no solution to cope with this situation.